Details of a Researcher - HIRAYAMA Takashi

HIRAYAMA Takashi

写真a

Affiliation	IWATE University Faculty of Science and Engineering Department of Systems Innovation Engineering Studies in Computer, Intelligence and Media Sciences
Position	Lecturer

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Research Interests 【 display / non-display 】

Logic minimization algorithms
Testing of logic circuits
Logic synthesis of VLSIs

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Graduating School 【 display / non-display 】

　

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1994.03

Gunma University Faculty of Engineering Computer Science Graduated

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Graduate School 【 display / non-display 】

　

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1996.03

Gunma University Graduate School, Division of Engineering Computer Science Master's Course Completed
　

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1999.03

Gunma University Graduate School, Division of Engineering Electronics and Computer Science Doctor's Course Completed

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Degree 【 display / non-display 】

Gunma University - Dr. Eng. 1999.01.01

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Campus Career 【 display / non-display 】

2016.04

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Now

IWATE University Faculty of Science and Engineering Department of Systems Innovation Engineering Studies in Computer, Intelligence and Media Sciences Lecturer [Duty]
2009.04

-

2016.03

IWATE University Faculty of Engineering Department of Electrical Engineering, Electronics and Computer Science Lecturer [Duty]
2001.04

-

2009.03

IWATE University Faculty of Engineering Computer and Information Sciences Lecturer [Duty]

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External Career 【 display / non-display 】

2000.04

-

2001.03

Ashikaga Institute of Technology Lecturer
1999.04

-

2000.03

Ashikaga Institute of Technology Research Assistant

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Research Areas 【 display / non-display 】

Informatics / Computer system

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Course Subject 【 display / non-display 】

2019

Advanced Logic Synthesis and Verification
2019

Advanced Training
2019

Advanced Research
2019

Advanced Logic Synthesis
2019

Selected Topics in Computer and Information Science

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Research Career 【 display / non-display 】

Study on Logic Synthesis of VLSIs Using Exclusive-OR Operations

Periods of research：

9999.01

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Now

Keywords : Logic Synthesis,Excusive OR,VLSI

Style of Research： Collaboration in Organization

Research Program： (not selected)
Study on Logic Optimization Algorithms

Periods of research：

9999.01

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Now

Keywords : Logic Optimization,Algorithm,Complexity

Style of Research： Collaboration in Organization

Research Program： (not selected)
Study on Easily Testable Realization of Logic Circuits

Periods of research：

9999.01

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Now

Keywords : Logic Circuits,Easy Testability,Logic Synthesis

Style of Research： Collaboration in Organization

Research Program： (not selected)

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Published Papers 【 display / non-display 】

Enumerating Empty and Surrounding Polygons

S. Terui, K. Yamanaka, T. Hirayama, T. Horiyama, K. Kurita, and T. Uno

IEICE Trans. Fundamentals ( IEICE ) E106-A ( 9 ) 1082 - 1091 2023.09 [Refereed]

Bulletin of University, Institute, etc. Multiple authorship

In this paper, we consider the problem of enumerating all the empty polygons of a given point set. We propose an algorithm that enumerates all the empty polygons of $S$. With this idea, we also propose an enumeration algorithm that enumerates the surrounding polygons.

DOI
Quick Computation of the Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits

：T. Hirayama, R. Suzuki, K. Yamanaka, and Y. Nishitani

Proc. 53rd IEEE International Symposium on Multiple-Valued Logic, Matsue, Japan ( IEEE ) 153 - 157 2023.05 [Refereed]

Others Multiple authorship

We present a time-efficient lower bound on the number of gates in Toffoli-based reversible circuits that represent a given reversible logic function. By slightly sacrificing the tightness of the lower bound, our lower bound achieves fast computation.
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs

T. Ito,Y. Sano,K. Yamanaka,T. Hirayama

IEICE Trans. Information and Systems ( IEICE ) E105-D ( 3 ) 466 - 473 2022.03 [Refereed]

Bulletin of University, Institute, etc. Multiple authorship

DOI
A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs

Yusuke Sano, Katsuhisa Yamanaka, and Takashi Hirayama

Proc. International Workshop on Frontiers in Algorithmics, FAW 2020, Haikou, China, LNCS 12340 13 - 24 2020.10 [Refereed]

Bulletin of University, Institute, etc. Multiple authorship

DOI
Exact Exponential Algorithm for Distance-3 Independent Set Problem

K. Yamanaka, S. Kawaragi, and T. Hirayama

IEICE Trans. Information and Systems E102-D ( 3 ) 499 - 501 2019.03 [Refereed]

Academic Journal Multiple authorship

DOI