HIRAYAMA Takashi

写真a

Affiliation

IWATE University  Faculty of Science and Engineering  Department of Systems Innovation Engineering  Studies in Computer, Intelligence and Media Sciences  

Position

Lecturer
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Research Interests 【 display / non-display 】

  • Testing of logic circuits

  • Logic minimization algorithms

  • Logic synthesis of VLSIs

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Graduating School 【 display / non-display 】

  • 　
    -
    1994.03

    Gunma University   Faculty of Engineering   Computer Science   Graduated

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Graduate School 【 display / non-display 】

  • 　
    -
    1996.03

    Gunma University  Graduate School, Division of Engineering  Computer Science  Master's Course  Completed

  • 　
    -
    1999.03

    Gunma University  Graduate School, Division of Engineering  Electronics and Computer Science  Doctor's Course  Completed

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Degree 【 display / non-display 】

  • Gunma University -  Dr. Eng.  1999.01.01

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Campus Career 【 display / non-display 】

  • 2016.04
    -
    Now

    IWATE University   Faculty of Science and Engineering   Department of Systems Innovation Engineering   Studies in Computer, Intelligence and Media Sciences   Lecturer   [Duty]

  • 2009.04
    -
    2016.03

    IWATE University   Faculty of Engineering   Department of Electrical Engineering, Electronics and Computer Science   Lecturer   [Duty]

  • 2001.04
    -
    2009.03

    IWATE University   Faculty of Engineering   Computer and Information Sciences   Lecturer   [Duty]

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External Career 【 display / non-display 】

  • 2000.04
    -
    2001.03

    Ashikaga Institute of Technology   Lecturer  

  • 1999.04
    -
    2000.03

    Ashikaga Institute of Technology   Research Assistant  

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Research Areas 【 display / non-display 】

  • Informatics / Computer system

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Course Subject 【 display / non-display 】

  • 2019

    Advanced Logic Synthesis and Verification

  • 2019

    Selected Topics in Computer and Information Science

  • 2019

    Logic Circuits

  • 2019

    Discrete Mathematics

  • 2019

    Advanced Training

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Research Career 【 display / non-display 】

  • Study on Logic Optimization Algorithms

    Periods of research：

    9999.01
    -
    Now

    Keywords : Logic Optimization,Algorithm,Complexity

    Style of Research： Collaboration in Organization

    Research Program： (not selected)  

  • Study on Easily Testable Realization of Logic Circuits

    Periods of research：

    9999.01
    -
    Now

    Keywords : Logic Circuits,Easy Testability,Logic Synthesis

    Style of Research： Collaboration in Organization

    Research Program： (not selected)  

  • Study on Logic Synthesis of VLSIs Using Exclusive-OR Operations

    Periods of research：

    9999.01
    -
    Now

    Keywords : Logic Synthesis,Excusive OR,VLSI

    Style of Research： Collaboration in Organization

    Research Program： (not selected)  

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Published Papers 【 display / non-display 】

  • A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs

    T. Ito,Y. Sano,K. Yamanaka,T. Hirayama

    IEICE Trans. Information and Systems ( IEICE )  E105-D ( 3 ) 466 - 473   2022.03  [Refereed]

    Bulletin of University, Institute, etc.  Multiple authorship

    DOI

  • A Polynomial Delay Algorithm for Enumerating 2-Edge-Connected Induced Subgraphs

    Yusuke Sano, Katsuhisa Yamanaka, and Takashi Hirayama

    Proc. International Workshop on Frontiers in Algorithmics, FAW 2020, Haikou, China, LNCS 12340     13 - 24   2020.10  [Refereed]

    Bulletin of University, Institute, etc.  Multiple authorship

    DOI

  • Exact Exponential Algorithm for Distance-3 Independent Set Problem

    K. Yamanaka, S. Kawaragi, and T. Hirayama

    IEICE Trans. Information and Systems   E102-D ( 3 ) 499 - 501   2019.03  [Refereed]

    Academic Journal  Multiple authorship

    DOI

  • Function design for minimum multiple-control Toffoli circuits of reversible adder/subtractor blocks and arithmetic logic units

    M. B. Ali, T. Hirayama, K. Yamanaka, and Y. Nishitani.

    IEICE Trans. Fundamentals of Electronics, Communications and Computer Sciences   E101-A ( 12 )   2018.12  [Refereed]

    Bulletin of University, Institute, etc.  Multiple authorship

  • Optimal Multiple-Control Toffoli Circuits of Reversible Adder-Subtractors and Reduced Quantum Gate Realization

    M. B. Ali, T. Hirayama, K. Yamanaka, and Y. Nishitani

    Proc. Reed-Muller Workshop 2017     2017.05  [Refereed]

    Bulletin of University, Institute, etc.  Multiple authorship

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Presentations 【 display / non-display 】

  • A testable design for decimal multiplication circuits

    Oral Presentation(Guest/Special)  Takashi Hirayama

    2010.10
    　
    　

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Academic Awards Received 【 display / non-display 】

  • 2019.11.20

  • 2019.09.21

  • 2018.11.14

  • 2018.09.23

  • 2017.06.07

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Association Memberships 【 display / non-display 】

  • 1997.01
    　
    　
     

    IPS Japan

  • 1996.01
    　
    　
     

    IEEE

  • 1995.01
    　
    　
     

    IEICE

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Academic Activity 【 display / non-display 】

  • 2022.04
    -
    2024.03

    IEICE  

  • 2020.10
    -
    2022.09

    IEICE  

  • 2020.04
    -
    2022.03

    IEICE  

  • 2018.10
    -
    2020.09

    IEICE  

  • 2018.04
    -
    2020.03

    IEICE  

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